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Silicon Labs /EFR32BG22C222F352GN32 /EUART0_S /TIMINGCFG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TIMINGCFG

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https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/EUART0_S/TIMINGCFG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NONE)TXDELAY

TXDELAY=NONE

Description

No Description

Fields

TXDELAY

TX Delay Transmission

0 (NONE): Frames are transmitted immediately.

1 (SINGLE): Transmission of new frames is delayed by a single bit period.

2 (DOUBLE): Transmission of new frames is delayed by a two bit periods.

3 (TRIPPLE): Transmission of new frames is delayed by a three bit periods.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data